View PPC405EZ-CSAFFFTX_4115176.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Part Number 405EZ Revision 1.27 - August 22, 2007
405EZ
PowerPC 405EZ Embedded Processor
Features
* AMCC PowerPC(R) 405 32-bit RISC processor core operating at up to 416MHz * On-chip 32-bit peripheral bus (OPB) operating at up to 83 MHz * On-chip 64-bit processor local bus (PLB) operating at up to 166MHz * 8-bit direct interface for NAND Flash devices * 32KB of on-chip, high-speed SRAM accessible by CPU and DMA * Inter-chip connectivity (SPI and IIC)
Preliminary Data Sheet
* IEEE 1588 Precision Timing Protocol (PTP) controller * Chameleon TimerTM and pulse width modulator (PWM) * Analog-to-Digital Converter (ADC) with eight inputs and 10-bit resolution at 300k samples/sec * Digital-to-Analog Converter (DAC) with one input and 10-bit resolution at 30M samples/sec * Two CAN 2.0B protocol and ISO 11898-1 compliant channels * Two serial ports (16750 compatible UART)
* External 8-,16-, or 32-bit peripheral bus (EBC) operating at up to 83MHz * Boot from IIC bootstrap controller, EBC, NAND Flash, and SPI * DMA support for all on-chip slaves and external bus, including on-chip SRAM, ADC, DAC, UARTs, and devices on the external peripheral bus * One 10/100 Mbps Ethernet MII interface (half- and full-duplex) to external PHY * Three USB 1.1 ports: two Host and one Device with Full-Speed on-chip PHYs * Programmable universal interrupt controller (UIC)
* One IIC interface operating at up to 400kHz and supporting all standard IIC EEPROMs * One SPI (SCP) synchronous full-duplex channel operating at up to 40 MHz * 54 general purpose I/Os (GPIOs), each with programmable interrupts and outputs * Supports JTAG for board-level testing * System power management, low power dissipation and small form factor * RoHS compliant (lead-free)
Description
With speeds up to 416MHz, a flexible on-chip and offchip memory architecture, a combination of an ADC, a DAC, a programmable Chameleon Timer/PWM, an IEEE 1588 PTP, and a diverse communications package that includes USB 1.1, Ethernet, and CAN, the PowerPC 405EZ embedded processor provides a low power and small footprint system-on-a-chip solution for a wide range of high performance, costconstrained embedded applications. This includes industrial control, high-precision AC/DC and servo drive control, instrumentation, data acquisition, industrial automation, building and enclosure management, commercial and retail systems, Internet
AMCC Proprietary
appliances, and intelligent USB peripherals. It is an easily programmable general purpose, 32-bit RISC controller that offers an upgrade path for applications in need of performance and connectivity improvements. Technology: CU-11 CMOS, 130nm Package: 324-ball, 23 mmx23 mm, lead-free, plastic ball grid array (EPBGA), 1mm ball pitch Typical Power (Est.): 1.05W @ 166 MHz;1.48W @ 416 MHz
1
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Power PC 405 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 On-Chip Memory (OCM) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 NAND Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Controller Area Network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Serial Peripheral Interface (SPI/SCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chameleon Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 General Purpose I/O (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 10/100 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 IEEE 1588 Precision Timing Protocol Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Digital-to-Analog Converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Signal Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Ratings and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
List of Figures
Figure 1. PPC405EZ Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. 23mm, 324-Ball EPBGA Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 3. Clocking Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 4. Input Setup and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 5. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
List of Tables
Table 1. System Memory Address Map (4GB System Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4. Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 5. Pin Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 6. Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 8. Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 10. Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 11. Typical DC Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 12. DC Power Supply Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 13. System Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 14. Peripheral Interface I/O Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 15. I/O Specifications--All CPU Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 16. I/O Specifications--416 MHz CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 17. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
AMCC Proprietary
3
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Ordering, PVR, and JTAG Information
This section provides the part number nomenclature. For availability, contact your local AMCC sales office.
Order Part Number (see Notes:) PPC405EZ-CSAFFFTX Rev Level A
Product Name PPC405EZ Notes: 1. 2. 3. 4.
Package 23mm, 324-ball, EPBGA
PVR Value 0x41511460
JTAG ID 0x0405A1E1
C = CAN enabled S = Lead-free EPBGA package (RoHS compliant) A = Chip revision level A fff = Processor frequency 166 = 166MHz 266 = 266MHz 333 = 333MHz 416 = 416MHz 5. T = Case temperature range, -40C to +105C 6. x = Shipping package type Z = tape-and-reel blank = tray
The part number contains a part modifier. Included in the modifier is a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain information that uniquely identifies the part. See the PPC405EZ Embedded Processor User's Manual for details about accessing these registers. Order Part Number Key
PPC405EZ-CSA416TZ
Shipping Package AMCC Part Number
Case Temperature Range Processor Speed (MHz)
CAN enabled
Package
Revision Level
Note: The example P/N above is CAN enabled, lead-free, capable of running at 416MHz, and is shipped in tape-and-reel packaging.
4
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Block Diagram
Figure 1. PPC405EZ Embedded Controller Functional Block Diagram
Universal Interrupt Controller
Clock Control Reset
Power Mgmt
32KB SRAM
Timers MMU PowerPC 405 Core JTAG
D-OCM I-OCM DCRs
OCM Ctrl UART x2 Arbiter On-chip Peripheral Bus (OPB) CAN x2 IIC/ BSC SPI GPIO Timer/ DAC (SCP) PWM ADC
DCR
Bus
Trace
16KB D-Cache 16KB I-Cache DMA Controller (4-Channel) OPB/PLB Bridges MAL Ethernet 10/100 USB 1.1 Host/Dev IEEE 1588 PTP
Arbiter
Processor Local Bus (PLB) 64 bit, PLB3 PHY External Bus Controller NAND Flash Controller
MII
The PPC405EZ is designed using the IBM Microelectronics Blue LogicTM methodology in which major functional blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture.
AMCC Proprietary
5
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Address Maps
The PPC405EZ incorporates two address maps. The first address map defines the possible use of addressable memory regions that the processor can access. The second address map defines Device Configuration Register (DCR) addresses (numbers). The DCRs are accessed by software running on the PPC405EZ processor through the use of mtdcr and mfdcr instructions. Table 1. System Memory Address Map (4GB System Memory)
Function General Use Reserved UART 0 Registers UART 1 Registers IIC Registers OPB Arbiter Registers GPIO 0 Controller Registers GPIO 1 Controller Registers EMAC Registers Reserved CAN 0 Registers CAN 1 Registers Chameleon Timer Registers IEEE 1588 Sync Controller Registers USB 1.1 Host Registers Reserved DAC Registers ADC Registers Serial Communication Port Registers Reserved USB 1.1 Device Registers Reserved Boot Address Range Notes: 1. If peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above. 2. After the boot process, software may reassign the boot memory regions for other uses. Subfunction Start Address 0x 0000 0000 0x E000 0000 0x EF60 0300 0x EF60 0400 0x EF60 0500 0x EF60 0600 0x EF60 0700 0x EF60 0800 0x EF60 0900 0x EF60 0A00 0x EF60 1000 0x EF60 1800 0x EF60 2000 0x EF60 2800 0x EF60 3000 0x EF60 3200 0x EF60 3300 0x EF60 3400 0x EF60 3500 0x EF60 3600 0x EF64 0000 0x EF68 0000 0x FFE0 0000 End Address 0x DFFF FFFF 0x EF60 02FF 0x EF60 03FF 0x EF60 04FF 0x EF60 05FF 0x EF60 06FF 0x EF60 07FF 0x EF60 08FF 0x EF60 09FF 0x EF60 0FFF 0x EF60 17FF 0x EF60 1FFF 0x EF60 27FF 0x EF60 2FFF 0x EF60 31FF 0x EF60 32FF 0x EF60 33FF 0x EF60 34FF 0x EF60 35FF 0x EF63 FFFF 0x EF67 FFFF 0x FFDF FFFF 0x FFFF FFFF 2 MB 262KB 256B 256B 256B 2KB 2KB 2KB 2KB 512B 256B 256B 256B 256B 256B 256B 256B Size 3.7GB
6
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 2. DCR Address Map
Function Total DCR Address Space Reserved CPR SDR Reserved EBC Reserved OCM Controller Reserved PLB Arbiter Reserved PLB-to-OPB Bridge Reserved OPB-to-PLB Bridge Reserved CPM Reserved UIC Reserved IEEE 1588 Snapshot Source Reserved DMA Reserved MAL Notes: 1. DCR address is 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register, or 1 kiloword (KW) (which equals 4 KB).
1
Start Address 0x000 0x000 0x00C 0x00E 0x010 0x012 0x014 0x020 0x030 0x080 0x090 0x0A0 0x0A8 0x0B0 0x0B4 0x0B8 0x0BC 0x0C0 0x0D0 0x0E0 0x0F0 0x100 0x140 0x380
End Address 0x3FF 0x00B 0x00D 0x00F 0x011 0x013 0x01F 0x02F 0x07F 0x08F 0x09F 0x0A7 0x0AF 0x0B3 0x0B7 0x0BB 0x0BF 0x0CF 0x0DF 0x0EF 0x0FF 0x13F 0x2FF 0x3FF
Size 1KW (4KB)1 12B 2B 2B 2B 2B 12B 16B 80B 16B 16B 8B 8B 4B 4B 4B 4B 16B 16B 16B 16B 64B 578B 128B
AMCC Proprietary
7
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Power PC 405 Processor Core
The PPC405 core is a fixed-point, 32-bit RISC processor. Features include: * Five-stage pipeline with single-cycle execution of most instructions, including loads and stores * Separate, configurable 16 KB D- and I-caches, both 2-way set associative * Thirty-two 32-bit general purpose registers (GPRs) * Unaligned load/store support * Hardware multiply/divide * Parity detection and reporting for the instruction cache, data cache, and translation look-aside buffer (TLB) * Double word instruction fetch from cache * Translation of the 4GB logical address space into physical addresses * On-chip memory (OCM) interface * Built-in timer and debug support * Power management * 32-bit DCR interface
Internal Buses
The PPC405EZ contains three internal buses: the on-chip peripheral bus (OPB), the processor local bus (PLB), and the device control register (DCR) bus. High bandwidth devices such as the processor and the DMA core utilize the PLB. Lower bandwidth I/O interfaces such as communications and timer interfaces utilize the OPB. OPB The OPB provides 32-bit address and data interfaces, and operates up to 83MHz. There is a bridge between the OPB and the PLB. Features include: * - Pipelined read support * - Dynamic bus sizing * - Single-cycle data transfer between masters and slaves PLB The Processor Local Bus (PLB) is a high-performance on-chip bus used to connect PLB-equipped master and slave devices to the PPC405 CPU. It provides a 64-bit data path with 32-bit addressing and operates at up to166MHz. There is a bridge between the PLB and the OPB. Features include: * Overlapping read and write transfers * Decoupled address and data buses * Address pipelining * Late master request abort capability * Hidden (overlapped) bus request/grant protocol * Bus arbitration-locking mechanism * Byte-enable capability allows for unaligned half word transfers and 3-B transfers * Support for 16-, 32-, and 64-B line data transfers * Read word address capability * Sequential burst protocol * Guarded and unguarded memory transfers * DMA buffered, flyby, peripheral-to-memory, memory-to-peripheral, and DMA memory-to-memory operations
8
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
DCR Bus The daisy-chained DCR bus provides a path for passing status and control information between the processor core and the other on-chip cores. All DCRs are 32 bits in width.
On-Chip Memory (OCM) Controller
The OCM controller connects the 405EZ processor core to two non-overlapping banks of single-port, on-chip, configurable 32KB SRAM memory. The OCM can also transfer data between the PLB and internal SRAM banks. Features include: * Simultaneous PLB3, instruction-Side OCM and data-Side OCM access * PLB slave cycles support: - 64-bit slave attachment addressable by any PLB master - Single-beat read and write (1 to 8 bytes) - 4-, 8-, and 16-word line read and write - Double word and word read and write bursts - Slave-terminated double word and word bursts - Master-terminated variable length bursts - Data parity generation and checking - Read/Write protection per bank * Instruction side interface supports: - One-Wait state OCM access with 1-deep write buffer - Data parity checking * Data side interface supports: - One-wait state OCM access with 1-deep write buffer - Data parity generation and checking - Read/Write protection per bank * Processor side data port has highest access priority (maintains predictable memory accesses to OCM)
External Bus Controller
The external bus controller (EBC) transfers data between the PLB and external memory or peripheral devices attached to the external peripheral bus. The EBC provides direct attachment of memory devices such as ROM and SRAM, DMA device paced memory devices, and DMA peripheral devices. Features include: * Up to 83 MHz speed * 8-, 16-, or 32-bit data bus, 28-bit address bus * Up to eight chip selects * Arbitration and multi-master supported * Flash ROM interface * Boot from EBC (including NAND Flash interface) support * Direct support for 8-,16-, or 32-bit SRAM and external peripherals * CRAM/PSRAM support
NAND Flash Controller
The NAND Flash controller (NDFC) provides a simple interface between the External Bus Controller (EBC) and a variety of NAND Flash-based storage devices. Features include: * Attachment as internal EBC slave device (refer to the PPC405EZ Embedded Processor User's Manual for
AMCC Proprietary
9
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
* * * * * * * * more details) Direct 8-bit interfacing to discrete NAND Flash devices Up to four banks of NAND Flash supported Device size 4MB-256MB (32Mb to 2Gb) supported 512B + 16B or 2kB + 64B device page sizes supported ECC generation - hamming code, single-bit correction, double-bit detection (SEC/DED) Eight-bit command write, address write, and data read/write Interrupt on device ready (after long page write or block erase operations) Boot from NAND - Executes up to 4 KB of boot code out of first block - Automatic page read accesses performed based on device configuration and read address
DMA Controller
The Direct Memory Access (DMA) controller is a Processor Local Bus (PLB) master that enables faster data transfer between memory and peripherals than is possible under program control. The 4-channel DMA controller handles data transfers between memory and peripherals and from memory-to-memory. Each channel has an independent set of registers needed for data transfer: a control register, a source address register, a destination address register, and a transfer count register. Features include: * Memory-to-memory transfers * Buffered memory-to-peripheral transfers * Buffered peripheral-to-memory transfers * Four independent DMA channels * Scatter/gather capability for dynamically programming multiple DMA transfers * Programmable address increment or decrement * Internal data buffering * Can transfer data to/from any PLB and OPB slave, including OCM and external bus
USB Interface
The USB support provides separate Host and Device interfaces compliant with the USB1.1 Specification Features include: * USB1.1 Host (2 ports) - Compliant with USB 1.1 Specification and OHCI version 1.0a Host Controller Specification - Compatible with USB 2.0 Full-Speed peripherals - Supports Low-Speed (1.5Mbps) operation - All transfer types (Isochronous, Interrupt, Control, and Bulk) supported - Tx and Rx FIFOs: 16-entries x 32-bits each - Independent 32-bit OPB master and slave interfaces (master and slave can operate asynchronously) - Programmable OPB slave base address - Up to 127 connected devices supported * USB1.1 Device (1 port) - Full- and Low-Speed device controller - 32-bit, OPB slave interface - Three Endpoints supported (Endpoint 0 is used for control) * Endpoints 1-2 can be IN, OUT, IN and OUT, IN/OUT programmable * Endpoints 1-2 configurable to support Interrupt/Bulk only, Isochronous only, Interrupt/Bulk or Isochronous (programmable) transfer types * Endpoints 1-2 configurable to support maximum packet size of 8, 16, 32, or 64 bytes * Endpoint 0 configurable to support maximum packet size of 8 or 16 bytes * Full Speed (12 Mbps) USB PHY for each of the 3 USB ports - Tolerates shorting to 5.25V and shorting to ground if driving signal conditions meet those specified in the
10 AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Universal Serial Bus Specification
Controller Area Network (CAN)
The CAN controller module supports the concept of mailboxes. It contains 32 receive buffers, each one with its own message filter, and 32 transmit buffers with a prioritized arbitration scheme. For optimal support of Higher Level Protocols (HLP) such as DeviceNet or SDC, the message filter covers the first two data bytes. Features include: * CAN 2.0B protocol compliant * ISO 11898-1 compliant * 32 Transmit message holding registers, programmable priority arbitration * Message abort command supported * 32 Receive buffers (each with own message filter) - Message filtering: ID, IDE, Remote Transmission Request (RTR), data byte 1, and data byte 2 * Message buffers can be linked together to build bigger message arrays * Automatic RTR response handler * Message Abort command supported * Maximum baud rate of 1Mbps with 8MHz system clock * Listen-only for debugging supported * Global masking supported * 32-bit OPB slave interface * Internal loopback
UART
The Universal Asynchronous Receiver/Transmitter (UART) interface provides two ports. The UART performs serial-to-parallel conversion on data received from a peripheral device or a modem, and parallel-to-serial conversion on data received from the processor. Features include: * Two ports (UART_0 and UART_1) * Software modem control functions (CTS, RTS, DSR, DTR, RI, DCD) on UART_0 * Programmable auto flow (data flow controlled by RTS and CTS signals) * 5-, 6-, 7-, or 8-bit characters * Programmable start, stop, parity bit insertion * 64 byte FIFOs to buffer Tx and Rx data * LIN sub-bus specification compliant - line break generation/detection and false start bit detection * Programmable internal/external loopback capabilities * Low Power and Sleep mode * Register conformance (after reset) to configuration of the NS16450 register set * Hold and shift registers (eliminate need for precise synchronization between processor and serial data in character mode) * Complete status reporting * Full prioritized interrupt system controls * Independently controlled transmit, receive, line status, and data set interrupts * Programmable baud generator (divides serial clock input and generates 16x clock) * Ability to add/delete standard asynchronous communication bits such as start, stop, and parity to/from serial data * Even, odd, or no-parity bit generation and detection * 1-, 1.5-, or 2-stop bit generation * Variable baud rate * Internal diagnostic capability
AMCC Proprietary
11
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
* Loopback controls for isolating communications link faults * Break, parity, overrun, framing error simulation * OPB interface with optional DMA support
IIC Bus Interface
The Inter-Integrated Circuit (IIC) interface provides a Philips I2C(R) compatible interface operating up to 400kHz either as a master, a slave, or both with a bootstrap controller (BSC) included. During chip reset, the bootstrap controller can read configuration data from an IIC compatible memory device (e.g., EEPROM). This data can be used to replace the default configuration settings provided by the chip. Features include: * One IIC channel * Compliant with Philips Semiconductors I2C Specification, dated 1995 * 100 kHz or 400 kHz operation * 8-bit data * 10- or 7-bit address * Slave Transmit and Receive * Master Transmit and Receive * Multiple bus masters supported * Programmable as master, slave, or master/slave * Boot parameters read from IIC attached memory with IIC bootstrap controller * 32-bit OPB slave interface
Serial Peripheral Interface (SPI/SCP)
The Serial Peripheral Interface (SPI) (also known as the Serial Communications Port or SCP) is a full-duplex, synchronous, character-oriented (byte) port that allows the exchange of data with other serial devices. The SPI is a master on the serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB. Features include: * One SPI/SCP channel, full duplex synchronous * SPI/SCP master * Up to 40 MHz * Programmable internal loopback capabilities * Multi-master protocol supported * Independent masking of all interrupts (master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, receive FIFO overflow) * Dynamic control of serial bit rate of data transfer (serial-master mode only) * Data Item size for each data transfer under programmer control (4-to-16 bits) * Boot from SPI supported * 32-bit OPB slave interface
12
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Chameleon Timer
The Chameleon Timer's Timer Service Engine (TSE) controls the local Timer RAM configured as 120 32-bit words and up to fifteen 24-bit timer channels, each with an Input Capture Register or an Output Compare Register. The Chameleon Timer interfaces to the OPB. Features include: * Pulse Width Modulation (PWM) and space vector PWM functions with non-overlap times - Programmable "deadband" intervals - Pulse period measurement - 48-bit input capture function - 48-bit output compare function - IEEE1588 time stamps - Automatic up, down, and up-then-down counting with modulus * Autonomous Timer Service Engine (TSE) manages timer channels - CPU programs "registers" in Timer SRAM (120x32 bits) * 15 timer channels + 1 timebase channel * Pulse period measurements * Configurable for seven 48-bit channels or 15 24-bit channels * Up to two timebases available simultaneously - Each time base has four optional sources: three internal (Timebase A, Timebase B, and IEEE1588) and one external * Speed/resolution: 166MHz counter, 2-clock (20ns) minimum period * Latency: 0.49sec worst case (based on 133MHz system clock) * External "Fault" pin to automatically disable timer channel outputs * Low EMC switching noise * Unused Timer I/O pins available for GPIO use * 32-bit OPB slave interface
General Purpose I/O (GPIO) Controller
The GPIO controller enables multiplexing of module I/O pins with multiple functions within the chip. That is, a single package pin can be assigned to multiple I/O functions. Which function the pin is assigned to is determined by register bit settings controlled by software. This significantly reduces the number of package pins needed to support multiple I/O groups. Features include: * Up to 54 GPIOs available - GPIOs are multiplexed with alternate functions - If not in use for dedicated functions, I/Os are available as GPIOs * Direct control of all functions from registers programmed by means of OPB bus master accesses * Time multiplexing of controller outputs to module outputs * Programmable conversion of module outputs to open-drain outputs (enables sharing of active low outputs externally) * Time multiplexing of module inputs to controller inputs
AMCC Proprietary
13
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the various sources of interrupts and the PPC405 processor. Features include: * 32 interrupt sources supported (5 external) * Generate interrupt on level (high or low) or edge (rising or falling) * Programmable as synchronous (edge-capture or level-sensitive) or asynchronous (edge- or level-sensitive triggering) * Each interrupt source/bit programmable as critical or non critical * 32-bit DCR bus interface * Optional interrupt handler vector generation - Programmable vector base address - Programmable vector offset size - Programmable interrupt priority ordering * Programmable polarity for all interrupt types * Interrupts of the same type do not need to be in contiguous bit positions * Status registers provide: current state of all interrupts, current state of enabled interrupts
10/100 Ethernet
The Ethernet support provides a single 10/100 Mbps interface. Features include: * ANSI/IEEE Std. 802.3 and IEEE 802.3u supplement compliant * Half-duplex and full-duplex supported * MII interface to external PHY * 512 byte receive FIFOs with programmable thresholds * FCS control for transmit/receive packets * Multiple packet handling in transmit and receive FIFOs * Unicast, multicast, broadcast, and promiscuous address filtering * Two 64-bit hash filters for unicast and multicast frames * Automatic retransmission of collided frames * Runt frame rejection * Programmable inter-frame gap * IEEE 802.3x compliant for frame-based flow control mechanism, including self-assembled control frame transmitting) * Wake-on-LAN and Power-over-Internet supported * Programmable internal/external loopback capabilities * 32-bit OPB slave (MAC) and PLB master (MAL) interfaces * Extensive error/status vector generation for each processed packet * VLAN tag ID supported (according to IEEE Draft 802.3ac/D1.0 standard) * Programmable automatic source address inclusion/replacement for transmit packets * Programmable automatic Pad/FCS stripping for receive packets * Programmable VLAN Tag inclusion/replacement for transmit packets
IEEE 1588 Precision Timing Protocol Controller
In a distributed control system containing multiple clocks, this feature defines messages used to exchange timing information for precision network synchronization purposes. A second UIC in the PPC405EZ is dedicated to generating snapshot triggers to the IEEE 1588 PTP controller from any interrupt source in the chip.
14
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Analog-to-Digital Converter (ADC)
The ADC is a mixed-signal core. It uses the successive approximation (binary search) conversion technique to achieve minimal conversion time. The analog input range is 0.0V to Vref. Features include: * Internal 10-bit resolution SAR ADC * Sample and hold * Support for multiple conversion times such as - 3.25 s with 4-MHz input clock - 52 s with 250-kHz input clock * Comparator * Digital controller * 8-channel analog input (3.3 V) with 8:1 analog multiplexer * 10-bit parallel digital outputs * Input trigger from Chameleon Timer supported * OPB interface with optional DMA support
Digital-to-Analog Converter (DAC)
The DAC is a 1-channel converter, optimized for low power applications. It provides unbuffered single-ended analog current output. The single analog current output can be tied directly to an output resistor to provide twoscomplementary, single-ended voltage outputs. Features include: * 10-bit resolution at 30M samples/sec * Segmented DAC * Single-ended current outputs (6mA maximum swing at 3.3V) * Monotonicity ensured * Straight binary input * Internal bandgap voltage reference * Power management by means of Sleep Mode * Integrated functional test logic * Input trigger from Chameleon Timer supported * OPB interface with optional DMA support
JTAG
Features include: * IEEE 1149.1 test access port * JTAG Boundary Scan Description Language (BSDL) Refer to http://www.amcc.com/Embedded/Partners for a list of AMCC partners supplying probes for use with the JTAG interface.
AMCC Proprietary
15
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Figure 2. 23mm, 324-Ball EPBGA Core
Gold Gate Release Corresponds to A01 Ball Location
Top View
Logo View
(R)
Part Number Lot Number
PPC405EZ
1YWWBZZZZZ
Epoxy Mold Compound PCB Substrate
2.65 max
0.3 - 0.6
23.0
Bottom View
21.0
23.0
AB AA Y W V U T R P N M L K J H G F E D C B A 01 03 05 07 09 11 13 15 17 19 21 02 04 06 08 10 12 14 16 18 20 22 0.60 0.1 SOLDERBALL x 324
1.0 TYP
Notes: 1. All dimensions are in mm. 2. Package is lead-free (RoHS compliant) 3. Package conforms to JEDEC SPEC.MS-034
16
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Signal Lists
The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. Multiplexed signals appear alphabetically multiple times in the list--once for each signal name on the ball. The Page column indicates the page within the table "Signal Functional Description" on page 35 on which the signals in the indicated interface group begin. Table 3. Signals Listed Alphabetically (Sheet 1 of 11)
Signal Name ADC_AGND ADC_AVDD ADC_In0 ADC_In1 ADC_In2 ADC_In3 ADC_In4 ADC_In5 ADC_In6 ADC_In7 ADC_InTrig[TS6][GPIO109] ADC_VRef BusReq[GPIO007] CAN0_Rx CAN0_Tx CAN0_TxE CAN1_Rx CAN1_Tx CAN1_TxE CRAM_AdV[GPIO010] CRAM_Clk[GPIO008] DAC_AGND DAC_AVDD DAC_CRef DAC_GRef DAC_IOutP DAC_IPTrig[TS5][GPIO108] DAC_IRRef DAC_VRef DebugEn DMAAck[GPIO027] DMAEOT/TC[GPIO026] DMAReq[GPIO025] EMCCOL EMCCRS EMCMDC EMCMDIO Ball AB07 AB08 T01 U01 W01 Y01 AA01 AB02 AB03 AB04 U04 AB06 D20 C02 B03 C01 C04 B04 A03 B22 F19 A07 A08 B08 B07 A06 C08 B09 B06 C17 A19 A20 C19 U02 J04 R03 N03 Ethernet 35 External Peripheral 38 System 49 Digital to Analog Converter (DAC) 37 External Peripheral Power 38 40 Controller Area Network 37 External Peripheral 38 Analog to Digital Converter (ADC) 37 Power Interface Group Page 40
AMCC Proprietary
17
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 2 of 11)
Signal Name EMCRxClk EMCRxDv EMCRxD0 EMCRxD1 EMCRxD2 EMCRxD3 EMCRxEr EMCTxClk EMCTxD0 EMCTxD1 EMCTxD2 EMCTxD3 EMCTxEn EMCTxEr Ball M01 R01 L02 L01 M02 N01 M03 R02 N02 P02 P03 P04 U03 T02 Ethernet 35 Ethernet 35 Interface Group Page
18
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 3 of 11)
Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball A01 A02 A05 A09 A14 A18 A22 B02 B21 C03 C09 C20 D04 D06 D08 D09 D12 D15 D19 E01 E22 H04 H19 J01 J09 J11 J12 J14 J22 K10 K11 K13 L04 L09 L11 L12 L13 L14 Power 40 Interface Group Page
AMCC Proprietary
19
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 4 of 11)
Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball M09 M10 M11 M12 M14 M19 N10 N12 N13 P01 P09 P11 P12 P14 P22 R04 R19 V01 V22 W04 W06 W08 W09 W11 W15 W19 Y03 Y06 Y20 AA02 AA04 AA05 AA21 AB01 AB05 AB09 AB14 AB18 AB22 Power 40 Interface Group Page
20
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 5 of 11)
Signal Name [GPIO000]PerCS4 [GPIO001]PerCS5[NFCE1] [GPIO002]PerCS6[NFCE2] [GPIO003]PerCS7[NFCE3] [GPIO004]HoldReq [GPIO005]HoldPri [GPIO006]HoldAck [GPIO007]BusReq [GPIO008]CRAM_Clk [GPIO009]PerReady [GPIO010]CRAM_AdV [GPIO011]NFCLE [GPIO012]NFData7 [GPIO013]NFData6 [GPIO014]NFData5 [GPIO015]NFData4 [GPIO016]NFData3 [GPIO017]NFData2 [GPIO018]NFData1 [GPIO019]NFData0 [GPIO020]NFALE [GPIO021]NFCE0 [GPIO022]NFRE [GPIO023]NFWE [GPIO024]NFRB [GPIO025]DMAReq [GPIO026]DMAEOT/TC [GPIO027]DMAAck [GPIO028]PWM_OE1[TS1O] [GPIO029]PWM_OE2[TS2O] [GPIO030]PWM_OE3[TS3] [GPIO031]PWM_8 Ball G20 F20 F21 E21 D22 D21 C22 D20 F19 C21 B22 W03 AA03 Y02 Y04 Y05 AA06 Y07 AA07 Y08 AA08 Y09 AA09 Y10 AA10 C19 A20 A19 B15 A15 C13 C11 System 49 Interface Group Page
AMCC Proprietary
21
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 6 of 11)
Signal Name [GPIO100]PWM_9 [GPIO101]PWM_10 [GPIO102]PWM_11 [GPIO103]PWM_12 [GPIO104]PWM_13 [GPIO105]PWM_14 [GPIO106]PWM_15 [GPIO107]PWM_DivClk[IRQ4] [GPIO108]DAC_IPTrig[TS5] [GPIO109]ADC_InTrig[TS6] [GPIO110]UART0_DCD [GPIO111]UART0_DSR [GPIO112]UART0_CTS [GPIO113]UART0_DTR[TmrClk][IEEE_1588TS] [GPIO114]UART0_RTS[SPI_SS_2] [GPIO115]UART0_RI[SPI_SS_3] [GPIO116][SPI_SS_In]SPI_SS1 [GPIO117]IRQ0[TrcClk] [GPIO118]IRQ1[TS1E] [GPIO119]IRQ2[TS2E] [GPIO120]IRQ3[TS4] GPIO121 Halt HoldAck[GPIO006] HoldPri[GPIO005] HoldReq[GPIO004] [IEEE_1588TS]UART0_DTR[TmrClk][GPIO113] IIC0SClk IIC0SData IRQ0[TrcClk][GPIO117] IRQ1[TS1E][GPIO118] IRQ2[TS2E][GPIO119] IRQ3[TS4][GPIO120] [IRQ4]PWM_DivClk[GPIO107] NFALE[GPIO020] NFCE0[GPIO021] [NFCE1]PerCS5[GPIO001] [NFCE2]PerCS6[GPIO002] [NFCE3]PerCS7[GPIO003] NFCLE[GPIO011] NFData0[GPIO019] NFData1[GPIO018] NFData2[GPIO017] NFData3[GPIO016] NFData4[GPIO015] NFData5[GPIO014] NFData6[GPIO013] NFData7[GPIO012] 22 Ball A10 B10 C10 C06 C07 B05 C05 A04 C08 U04 D02 D01 E03 F04 F03 E02 D14 T03 V02 V03 W02 C14 C18 C22 D21 D22 F04 B16 C15 T03 V02 V03 W02 A04 AA08 Y09 F20 F21 E21 W03 Y08 AA07 Y07 AA06 Y05 Y04 Y02 AA03 AMCC Proprietary NAND Flash 38 NAND Flash 38 NAND Flash 38 Interrupt 35 IEEE 1588 Network Synchronization IIC Peripheral 35 35 External Peripheral 38 System 36 System 49 Interface Group Page
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 7 of 11)
Signal Name NFRB[GPIO024] NFRE[GPIO022] NFWE[GPIO023] OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 Ball AA10 AA09 Y10 D05 D07 D11 D16 D18 E04 G04 J10 J13 K09 M04 N09 P10 T04 V04 W05 W07 E19 G19 K14 L19 N14 P13 T19 V19 W12 W16 W18 Power 40 Power 40 NAND Flash 38 Interface Group Page
AMCC Proprietary
23
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 8 of 11)
Signal Name PerAddr04 PerAddr05 PerAddr06 PerAddr07 PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerClk PerCS0 PerCS1 PerCS2 PerCS3 PerCS4[GPIO000] PerCS5[NFCE1][GPIO001] PerCS6[NFCE2][GPIO002] PerCS7[NFCE3][GPIO003] Ball U19 V20 W21 W22 U20 V21 U21 U22 T20 T21 T22 R20 P19 R21 R22 P20 P21 N20 N21 N22 M20 M21 M22 L22 L21 L20 K22 K21 K20 H20 G22 G21 F22 G20 F20 F21 E21 External Peripheral 38 External Peripheral 38 Interface Group Page
24
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 9 of 11)
Signal Name PerData00 PerData01 PerData02 PerData03 PerData04 PerData05 PerData06 PerData07 PerData08 PerData09 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 PerData27 PerData28 PerData29 PerData30 PerData31 PerOE PerReady[GPIO009] PerRW PerWBE0 PerWBE1 PerWBE2 PerWBE3 PLL_AGND PLL_AVDD PWM_DivClk[IRQ4][GPIO107] PWM_OE0 PWM_OE1[TS1O][GPIO028] PWM_OE2[TS2O][GPIO029] PWM_OE3[TS3][GPIO030] PWM_TBA Ball Y11 AA11 AA12 AB13 Y12 AA13 AB15 Y13 AA14 AA15 AB16 Y14 W14 AB17 Y15 AA16 Y16 AA17 AA18 Y17 Y18 AB19 W17 AA19 AB20 Y19 AA20 AB21 Y22 AA22 Y21 W20 E20 C21 J21 J20 H22 J19 H21 AB11 AB12 A04 A16 B15 A15 C13 B14 Chameleon Timer 36 Power Chameleon Timer 40 36 External Peripheral 38 External Peripheral External Peripheral External Peripheral 38 38 38 External Peripheral 38 Interface Group Page
AMCC Proprietary
25
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 10 of 11)
Signal Name PWM_1 PWM_2 PWM_3 PWM_4 PWM_5 PWM_6 PWM_7 PWM_8[GPIO031] PWM_9[GPIO100] PWM_10[GPIO101] PWM_11[GPIO102] PWM_12[GPIO103] PWM_13[GPIO104] PWM_14[GPIO105] PWM_15[GPIO106 Reserved SPI_ClkOut SPI_DI SPI_DO SPI_SS0 SPI_SS1[SPI_SS_In][GPIO116] [SPI_SS2]UART0_RTS[GPIO114] [SPI_SS3]UART0_RI[GPIO115] [SPI_SS_In]SPI_SS1[GPIO116] SysClk SysErr SysReset TCK TDI TDO TestEn TMS [TmrClk]UART0_DTR[IEEE1588TS][GPIO113] [TrcClk]IRQ0[GPIO117] TRST [TS1E]IRQ1[GPIO118] [TS2E]IRQ2[GPIO119] [TS1O]PWM_OE1[GPIO028] [TS2O]PWM_OE2[GPIO029] [TS3]PWM_OE3[GPIO030] [TS4]IRQ3[GPIO120] [TS5]DAC_IPTrig[GPIO108] [TS6]ADC_InTrig[GPIO109] Ball B13 C12 B12 A13 A12 A11 B11 C11 A10 B10 C10 C06 C07 B05 C05 B19 B17 D17 C16 A17 D14 F03 E02 D14 AB10 B20 B18 H01 L03 K03 A21 G02 F04 T03 G01 V02 V03 B15 A15 C13 W02 C08 U04 Trace 36 JTAG System Trace JTAG 35 36 36 35 JTAG 35 System 36 Serial Peripheral 38 Other Pins 40 Chameleon Timer 36 Interface Group Page
26
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 11 of 11)
Signal Name UART0_CTS[GPIO112] UART0_DCD[GPIO110] UART0_DSR[GPIO111] UART0_DTR[TmrClk][IEEE_1588TS][GPIO113] UART0_RI[SPI_SS_3][GPIO115] UART0_RTS[SPI_SS_2][GPIO114] UART0_Rx UART0_Tx UART1_Rx UART1_Tx USB_FClk USB1Dev0 USB1Dev0 USB1Host0 USB1Host0 USB1Host1 USB1Host1 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD Ball E03 D02 D01 F04 E02 F03 B01 D03 F02 F01 G03 K02 K01 H03 H02 J03 J02 D10 D13 K04 K12 K19 L10 M13 N04 N11 N19 W10 W13 Power 40 USB 39 UART Peripheral 39 UART Peripheral 39 Interface Group Page
AMCC Proprietary
27
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
In the following table, only the primary (default) signal name is shown for each ball. Multiplexed or multifunction signals are marked with an asterisk (*). To determine what signals or functions are multiplexed on those balls, look up the primary signal name in "Signals Listed Alphabetically" on page 17.The following table lists the signals by ball assignment. Table 4. Signals Listed by Ball Assignment (Sheet 1 of 6)
Ball A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 GND GND CAN1_TxE PWM_DivClk* GND DAC_IOutP DAC_AGND DAC_AVDD GND PWM_9* PWM_6 PWM_5 PWM_4 GND PWM_OE2* PWM_OE0 SPI_SS0 GND DMAAck* DMAEOT/TC* TestEn GND Signal Name Ball B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 Signal Name UART0_Rx GND CAN0_Tx CAN1_Tx PWM_14* DAC_VRef DAC_GRef DAC_CRef DAC_IRRef PWM_10* PWM_7 PWM_3 PWM_1 PWM_TBA PWM_OE1* IIC0SClk SPI_ClkOut SysReset Reserved SysErr GND CRAM_AdV* Ball C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 Signal Name CAN0_TxE CAN0_Rx GND CAN1_Rx PWM_16* PWM_12* PWM_13* DAC_IPTrig* GND PWM_11* PWM_8* PWM_2 PWM_OE3* GPIO121 IIC0SData SPI_DO DebugEn Halt DMAReq* GND PerReady* HoldAck* Ball D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 Signal Name UART0_DSR* UART0_DCD* UART0_Tx GND OVDD1 GND OVDD1 GND GND VDD OVDD1 GND VDD SPI_SS1* GND OVDD1 SPI_DI OVDD1 GND BusReq* HoldPri* HoldReq*
28
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 2 of 6)
Ball E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 GND UART0_RI* UART0_CTS* OVDD1 No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD2 PerOE PerCS7* GND Signal Name Ball F01 F02 F03 F04 F05 F06 F07 F08 F09 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 Signal Name UART1_Tx UART1_Rx UART0_RTS* UART0_DTR* No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball CRAM_Clk* PerCS5* PerCS6* PerCS3 Ball G01 G02 G03 G04 G05 G06 G07 G08 G09 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 Signal Name TRST TMS USB_FClk OVDD1 No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD2 PerCS4* PerCS2 PerCS1 Ball H01 H02 H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 TCK USB1Host0 USB1Host0 GND No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball GND PerCS0 PerWBE3 PerWBE1 Signal Name
AMCC Proprietary
29
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 3 of 6)
Ball J01 J02 J03 J04 J05 J06 J07 J08 J09 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 GND USB1Host1 USB1Host1 EMCCRS No ball No ball No ball No ball GND OVDD1 GND GND OVDD1 GND No ball No ball No ball No ball PerWBE2 PerWBE0 PerRW GND Signal Name Ball K01 K02 K03 K04 K05 K06 K07 K08 K09 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 Signal Name USB1Dev0 USB1Dev0 TDO VDD No ball No ball No ball No ball OVDD1 GND GND VDD GND OVDD2 No ball No ball No ball No ball VDD PerClk PerAddr31 PerAddr30 Ball L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 Signal Name EMCRxD1 EMCRxD0 TDI GND No ball No ball No ball No ball GND VDD GND GND GND GND No ball No ball No ball No ball OVDD2 PerAddr29 PerAddr28 PerAddr27 Ball M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 Signal Name EMCRxClk EMCRxD2 EMCRxEr OVDD1 No ball No ball No ball No ball GND GND GND GND VDD GND No ball No ball No ball No ball GND PerAddr24 PerAddr25 PerAddr26
30
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 4 of 6)
Ball N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 Signal Name EMCRxD3 EMCTxD0 EMCMDIO VDD No ball No ball No ball No ball OVDD1 GND VDD GND GND OVDD2 No ball No ball No ball No ball VDD PerAddr21 PerAddr22 PerAddr23 Ball P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 GND EMCTxD1 EMCTxD2 EMCTxD3 No ball No ball No ball No ball GND OVDD1 GND GND OVDD2 GND No ball No ball No ball No ball PerAddr16 PerAddr19 PerAddr20 GND Signal Name Ball R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 Signal Name EMCRxDv EMCTxClk EMCMDC GND No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball GND PerAddr15 PerAddr17 PerAddr18 Ball T01 T02 T03 T04 T05 T06 T07 T08 T09 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Signal Name ADC_In0 EMCTxEr IRQ0* OVDD1 No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD2 PerAddr12 PerAddr13 PerAddr14
AMCC Proprietary
31
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 5 of 6)
Ball U01 U02 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 Signal Name ADC_In1 EMCCOL EMCTxEn ADC_InTrig* No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball PerAddr04 PerAddr08 PerAddr10 PerAddr11 Ball V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 GND IRQ1* IRQ2* OVDD1 No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD2 PerAddr05 PerAddr09 GND Signal Name Ball W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 Signal Name ADC_In2 IRQ3* NFCLE* GND OVDD1 GND OVDD1 GND GND VDD GND OVDD2 VDD PerData12 GND OVDD2 PerData22 OVDD2 GND PerData31 PerAddr06 PerAddr07 Ball Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Signal Name ADC_In3 NFData6* GND NFData5* NFData4* GND NFData2* NFData0* NFCE0* NFWE* PerData00 PerData04 PerData07 PerData11 PerData14 PerData16 PerData19 PerData20 PerData25 GND PerData30 PerData28
32
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 6 of 6)
Ball AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 Signal Name ADC_In4 GND NFData7* GND GND NFData3* NFData1* NFALE* NFRE* NFRB* PerData01 PerData02 PerData05 PerData08 PerData09 PerData15 PerData17 PerData18 PerData23 PerData26 GND PerData29 Ball AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 GND ADC_In5 ADC_In6 ADC_In7 GND ADC_VRef ADC_AGND ADC_AVDD GND SysClk PLL_AGND PLL_AVDD PerData03 GND PerData06 PerData10 PerData13 GND PerData21 PerData24 PerData27 GND Signal Name Ball Signal Name Ball Signal Name
AMCC Proprietary
33
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Pin Group List The following table provides a summary of the number of package pins (balls) associated with each functional interface group. Table 5. Pin Groups
Group
Total Signal Pins VDD OVDD1 OVDD2 GND ADC_AVDD ADC_GND DAC_AVDD DAC_GND PLL_AVDD PLL_GND Reserved Total Pins
No. of Pins
200 12 17 11 77 1 1 1 1 1 1 1 324
In the table "Signal Functional Description" on page 35, each external signal is listed along with a short description of the signal function. Active-low signals (for example, Halt) are marked with an overline. See the preceding table, "Signals Listed Alphabetically" on page 17, for the pin (ball) number to which each signal is assigned. Multiplexed Pins Some signals are multiplexed on the same package pin so that the pin can be used for different functions. In most cases, the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in "Signals Listed Alphabetically" on page 17. It is expected that in any single application a particular pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. Initialization Strapping One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see "Initialization" on page 51). Note that the use of these pins for strapping is not considered multiplexing since the strapping function is not programmable. Pull-Up and Pull-Down Resistors Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an appropriate state. The recommended pull-up value of 3k to +3.3V and pull-down value of 1k to GND, applies only to individually terminated signals. To prevent possible damage to the device, I/Os capable of becoming outputs must never be tied together and terminated through a common resistor. If your system-level test methodology permits, input-only signals can be connected together and terminated through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure that the grouped I/Os reach a valid logic zero or logic one state when accounting for the total input current into the PPC405EZ.
34
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Signal Functional Descriptions
The following table provides a description of the I/O signals on the PPC405EZ. Table 6. Signal Functional Description (Sheet 1 of 6)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required.
Signal Name Description I/O Type
Notes
Ethernet Interface
EMCCOL EMCCRS EMCMDC EMCMDIO EMCRxClk EMCRxDV EMCRxEr EMCRxD0:3 EMCTxClk EMCTxD0:3 EMCTxEn EMCTxEr Collision signal from the PHY. Carrier sense signal from the PHY. Management data clock to the PHY. Management data I/O between the Ethernet controller and the PHY. Input receive clock from the PHY. Receive data valid. Receive error from the PHY. Receive data from the PHY. EMCRxD3 is the msb. Input transmit clock from the PHY. Transmit data to the PHY. EMCTxD3 is the msb. Transmit enable. Transmit error to the PHY. I I O I/O I I I I I O O O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL Rcvr 3.3V LVTTL 3.3V LVTTL Rcvr 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 5 5 5 5
IEEE 1588 Network Synchronization Interface
IEEE_1588TS Test signal. O 3.3V LVTTL
IIC Peripheral Interface
IIC0SClk IIC0SData IIC Serial Clock. IIC Serial Data. I/O I/O 3.3V IIC 3.3V IIC 1, 5 1, 5
Interrupts Interface
IRQ0:4 Interrupt requests. I 3.3V LVTTL 1, 5
JTAG Interface
TCK TDI TDO TMS TRST Test clock. Test data in. Test data out. Test mode select. Test reset. Must be low at power-on to initialize the JTAG controller and for normal operation of the PPC405EZ. I I O I I 3.3V LVTTL Rcvr w/pull-up 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL Rcvr w/pull-up 5 5 5 5
AMCC Proprietary
35
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 2 of 6)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required.
Signal Name Description I/O Type
Notes
System Interface
SysClk SysErr SysReset TestEn DebugEn Halt TmrClk GPIO000:03 GPIO004:05 GPIO006:08 GPIO009 GPIO010:11 GPIO012:19 GPIO019:27 GPIO028:31 GPIO100:12 GPIO113:14 GPIO115:21 General purpose I/O. All of the GPIO signals are multiplexed with other signals. Which signal a pin is connected to depends on the setting of bits in the GPIO registers. System input clock. Machine check exception has occurred. Main system reset. This signal may be driven by the PPC405EZ to cause a board level reset to occur. Test enable. Reserved for manufacturing LSSD test. Debug enable. External request to stop the processor. Processor timer external input. I O I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 5 5 5 4 5 5 5 4
Trace Interface
TrcClk TS1E TS2E TS1O TS2O TS3:6 Trace interface clock. Operates at half the CPU core frequency. Even trace execution status. Odd trace execution status. Trace status. I I I I 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
Chameleon Timer Interface
PWM_DivClk PWM_OE0 PWM_OE1:3 PWM_TBA PWM_1:15 Divided-down clock. PWM 0 Output enable input. PWM 1:3 Output enable input. Time Base A. PWM Interface bus. O I I I/O I/O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 5 4
36
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 3 of 6)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required.
Signal Name Description I/O Type
Notes
Analog to Digital (ADC) Interface
ADC_In0:7 ADC_InTrig ADC_VRef Analog inputs. Analog inputs to the ADC should be referenced to ADC_AGND and should not exceed the value of VRef. Input trigger. Analog input reference voltage. Allowable voltage range is 2V-ADC_AVDD. I I I Analog WideWire receiver 3.3V LVTTL Analog WideWire receiver
Digital to Analog (DAC) Interface
DAC_CRef Reference voltage for the gate of the DAC current sources. This voltage should be connected to the DAC_AVDD voltage with a 1nF filter capacitor at the signal pin. Analog positive output current. Input trigger. Analog input reference current. Analog band gap voltage reference input. Allowable voltage range is 1.15V-1.26V, with a typical value of 1.174V. Reference voltage for the gate of the cascode device in the DAC current sources. This voltage should be connected to the DAC_AVDD voltage with a 1nF filter capacitor at the signal pin. I Analog WideWire driver Analog WideWire driver 3.3V LVTTL Analog WideWire driver Analog WideWire driver Analog WideWire driver
DAC_IOutP DAC_IPTrig DAC_IRRef
O I I
DAC_VRef
I
DAC_GRef
I
Controller Area Network Interface
CAN0_Rx CAN0_Tx CAN0_TxE CAN1_Rx CAN1_Tx CAN1_TxE Receive input. Transmit output. Transmit enable. Receive input. Transmit output. Transmit enable. I O O I O O 3.3V LVTTL Rcvr w/pull-up 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 5 5
AMCC Proprietary
37
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 4 of 6)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required.
Signal Name Description I/O Type
Notes
External Peripheral Interface
CRAM_AdV CRAM_Clk PerAddr04:31 BusReq PerClk PerCS0:7 PerData00:31 PerOE PerReady PerRW PerWBE0:3 DMAAck DMAEOT/TC DMAReq HoldReq HoldAck HoldPri Address valid signal for PSRAM/CRAM support. PerClk gated for PSRAM/CRAM support. Memory address bus 4:31. External PLB bus request. Clock output. Chip selects 0:7. Memory data bus 0:31. Output enable. Wait for PSRAM/CRAM support. Read/Write. Write bus enable 0:3. External DMA peripheral acknowledge. External DMA peripheral end-of-transmission/terminal count. External peripheral DMA request. External request for bus access. External request acknowledge. External bus request priority. O O O O O O I/O O I O O O I/O I I O I 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 5 5 5
NAND Flash Interface
NFALE NFCE0:3 NFCLE NFData0:7 NFRB NFRE NFWE Address latch enable. Cchip selects 0:3. Command latch enable. Data bits 0:7 Read/Busy. If low, indicates that Read/Erase command is in process. If high, indicates that the command is complete. Read enable. Write enable. O O O I/O I O O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
Serial Peripheral Interface
SPI_ClkOut SPI_DI SPI_DO SPI_SS0:3 SPI_SS_In Serial peripheral interface clock. Master and slave input. Master and slave output. Slave Select 0:3. Slave Select Input for multi-master collision detection. O I O O I 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 5
38
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 5 of 6)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required.
Signal Name Description I/O Type
Notes
UART Peripheral Interface
UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_Rx UART1_Tx Clear to send. Data carrier detect. Data set ready. Data terminal ready. Ring indicator. Request to send. Receive data. Transmit data. Receive data Transmit data I I I O I O I O I O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 5 5
USB Interface
USB1FClk USB1DEV0 USB1DEV0 USB1HOST0 USB1HOST0 USB1HOST1 USB1HOST1 48 MHz clock for USB Device differential + data signal Device differential - data signal Host 0 differential + data signal Host 0 differential - data signal Host 1 differential + data signal Host 1 differential - data signal I I/O I/O I/O I/O I/O I/O 3.3V LVTTL 5V tolerant USB Diff 5V tolerant USB Diff 5V tolerant USB Diff 5V tolerant USB Diff 5V tolerant USB Diff 5V tolerant USB Diff
AMCC Proprietary
39
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 6 of 6)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required.
Signal Name Description I/O Type
Notes
Power
VDD OVDD1 OVDD2 GND ADC_AVDD ADC_AGND Logic VDD supply. Non-EBC I/O VDD supply. EBC I/O VDD supply. System ground. ADC analog VDD supply. ADC analog ground. DAC analog VDD supply. It is recommended that this voltage be provided by means of a voltage supply and voltage plane separate from the logic voltage. DAC analog ground. PLL analog VDD supply. See "Absolute Maximum Ratings" on page 41 for filter recommendations. PLL analog ground. na na na na na na na na na na Analog WideWire receiver Analog WideWire receiver Analog WideWire receiver Analog WideWire receiver na na na na na na na na
DAC_AVDD
na
na
DAC_AGND PLL_AVDD PLL_AGND
na na na
na na na
Other Pins
Reserved Reserved pins. Do not make voltage, ground, or signal connections to these pins. na na na
40
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Ratings and Specifications
Table 7. Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device. None of the performance specification contained in this document are guaranteed when operating at these maximum ratings.
Characteristic Supply Voltage (Internal Logic) Non-EBC I/O Supply Voltage EBC I/O Supply Voltage PLL Analog Supply Voltage ADC Analog Supply Voltage DAC Analog Supply Voltage Input Voltage (3.3V LVTTL receivers) Input Voltage (5.0V LVTTL receivers) Storage Temperature Range Case temperature under bias Junction temperature Symbol VDD OVDD1 OVDD2 PLL_AVDD ADC_AVDD DAC_AVDD VIN VIN TSTG TC TJMax Value 0 to +1.6 0 to +3.6 0 to +3.6 0 to +1.6 0 to +3.465 0 to +3.465 0 to +3.6 0 to +5.5 -55 to +150 -40 to +120 +125 Unit V V V V V V V V C C C 3 Notes
1. All voltages are specified with respect to GND. 2. The analog voltages use for the system PLL, the ADC, and the DAC can be derived from VDD and OVDD1, but must be filtered as shown below before entering the PPC405EZ. Use a separate filter for each voltage. The maximum value for ADC_PLL and DAC_PLL must be limited to the values shown in this table. 3. OVDD2 must be limited to a maximum value of +3.3V if CRAM/PSRAM devices are attached to the EBC interface. This is a limitation imposed by the CRAM/PSRAM devices, not the PPC405EZ.
VDD L1 C1
PLL_AVDD
L1 - Murata BLM18AG121SN1D C1 - 0.1 F ceramic
PLL_AGND
GND OVDD1 L1 C1 C2 ADC_GND, DAC_GND ADC_PLL, DAC_PLL L1 - Murata BLM18AG121SN1D C1 - 0.1 F ceramic C2 - 0.01F ceramic
GND
AMCC Proprietary
41
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 8. Package Thermal Specifications
The PPC405EZ is designed to operate within a case temperature range of -40C to +105C. Thermal resistance values for the EPBGA packages in a convection environment are as follows:
Parameter Junction-to-ambient thermal resistance without heat sink Junction-to-ambient thermal resistance with heat sink Symbol 0 (0) 100 (0.51) 24.1 14.3 Airflow ft/min (m/sec) 200 (1.02) 22.9 12.3 300 (1.52) 22.4 11.5 400 (2.02) 22.0 11.1 600 (3.03) 21.6 10.7 C/W C/W Unit
JA JA JC JB
29.3 22.7
Resistance Value Junction-to-case thermal resistance Junction-to-board thermal resistance Notes: 1. Values in the table are achieved with the following JEDEC standard board: 114.5mm x 101.6mm x 1.6mm, 4 layers. 2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist: a. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board. b. TA = TC - Px CA, where TA is ambient temperature and P is power consumption. c. TC Max = TJ Max - PxJC, where TJMax is maximum junction temperature and P is power consumption. 3. Values with a heat sink were achieved with a 38.1mm x 38.1mm x 16.5mm unit, attached to the chip using a 0.1mm thickness of adhesive having a thermal conductivity of 1.3W/mK. 11.9 16.4 C/W C/W
Thermal Management The following heat sink was used in the above thermal analysis: Aavid Thermalloy, PN 79985 The heat sink is manufactured by: Aavid Thermalloy 70 Commercial St. Concord, NH 03301 USA Tel: (603)224-9988 URL: www.aavidthermalloy.com
42
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 9. Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability.
Parameter Logic Supply Voltage I/O Supply Voltage (for non-EBC I/O) I/O Supply Voltage (for EBC I/O) PLL Analog Supply Voltage ADC Analog Supply Voltage DAC Analog Supply Voltage I/O Input Low (3.3V LVTTL) I/O Input High (3.3V LVTTL) I/O Output Low (3.3V LVTTL) I/O Output High (3.3V LVTTL) I/O High (USB, 5V tolerant) I/O Low (USB, 5V tolerant) I/O Input High (IIC) I/O Input Low (IIC) I/O Output High (IIC) I/O Output Low (IIC) Input Leakage Current (no pull-up or pull-down) Input Leakage Current (with internal pull-down) I/O Maximum Allowable Overshoot (3.3V LVTTL) I/O Maximum Allowable Undershoot (3.3V LVTTL) Case Temperature Notes: 1. When using CRAM or PSRAM memory on the EBC interface, this voltage must be limited to a maximum of +3.3V. This is a limitation imposed by the CRAM/PSRAM devices, not the PPC405EZ. Symbol VDD OVDD1 OVDD2 PLL_AVDD ADC_AVDD DAC_AVDD VIL VIH VOL VOH VOH VOL VIH VIL VIH VOL IIL1 IIL2 VMAO VMAU TC -0.6 -40 +105 0 0 0 +0.4 0 200 +3.9 0.7OVDD -0.3 Minimum +1.425 +3.0 +3.0 +1.4 +3.135 +3.135 0 +2.0 0 +2.4 +2.8 +0.3 OVDD + 0.3 +0.3OVDD Typical +1.5 +3.3 +3.3 +1.5 +3.3 +3.3 Maximum +1.575 +3.6 +3.6 (see Note 1) +1.6 +3.465 +3.465 +0.8 +3.6 +0.4 +3.6 Unit V V V V V V V V V V V V V V V V 1 Notes
A A
V V C
Table 10. Input Capacitance
Parameter 3.3V LVTTL I/O USB 5V Tolerant I/O IIC I/O Symbol CIN1 CIN2 CIN3 Maximum 1.9 3.2 5.8 Unit pF pF pF Notes
AMCC Proprietary
43
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 11. Typical DC Power Supply Requirements
Frequency (MHz) 166 266 333 416 +1.5V Supply 0.81 0.97 1.13 1.2 +3.3V Supply 0.24 0.25 0.29 0.28 Total 1.05 1.22 1.42 1.48 Unit W W W W Notes 1 1 2 3
Table 12. DC Power Supply Loads
Parameter VDD (+1.5V) active operating current OVDD (+3.3V) active operating current AVDD (+1.5V) active operating current ADC_AVDD (3.3V) ADC input current DAC_AVDD (3.3V) DAC input current Notes: 1. Typical and Maximum values are estimates and subject to change. Symbol IDD IODD IADD IADCDD IDACDD Typical 425 60 20 7 7 Maximum 815 95 35 8 8 Unit mA mA mA mA mA Notes 1 1 1 1 1
Test Conditions Clock timing and switching characteristics are specified in accordance with minimum operating conditions shown in the table "Recommended DC Operating Conditions" on page 43. For all signals, AC specifications are characterized at TC = 85C with the 50pF test load shown in the figure to the right.
Output Pin
50pF
44
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 13. System Clocking Specifications
Symbol CPU PFC SysClk Input SCFC SCTCS SCTCH SCTCL SCRT TrcClk Output TCFC TCTCS Other Clocks VCOFC PLBFC OPBFC VCO frequency PLB frequency OPB frequency 600 33 33 1333.33 166 83 MHz MHz MHz Clock output frequency Clock edge stability (phase jitter, cycle to cycle) PFC/2 0.2 MHz ns Frequency Edge stability (phase jitter, cycle to cycle) Input high time Input low time Rise time 33.33 na 0.6 0.6 na 100 0.1 na na 0.4 MHz ns ns ns ns Processor clock frequency (must be SCFC) 133.33 416 MHz Parameter Min Max Units
Note: Input slew rate = 1V/ns
Figure 3. Clocking Waveform
2.0V 1.5V 0.8V TCH TC TCL
AMCC Proprietary
45
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Spread Spectrum Clocking
Care must be taken if using a spread spectrum clock generator (SSCG) with the PPC405EZ. This controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is called tracking skew. The PLL bandwidth and phase angle determine how much tracking skew exists between the SSCG and the PLL for a given frequency deviation and modulation frequency. If using an SSCG with the PPC405EZ the following conditions must be met: * The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the PPC405EZ with one or more internal clocks at their maximum supported frequency, the SSCG can only lower the frequency. * The maximum frequency deviation must not exceed -3%, and the modulation frequency must not exceed 40kHz. In some cases, on-board PPC405EZ peripherals impose more stringent requirements (see Note 1). * Use the peripheral bus clock for logic that is synchronous to the peripheral bus because this clock tracks the modulation. Notes: 1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur, assuming that the connected device is running at precise baud rates. If an external serial clock is used, baud rate is unaffected by the modulation. 2. Ethernet operation is unaffected. 3. IIC operation is unaffected. Caution: The system designer must ensure that any SSCG used with the PPC405EZ meets these requirements and does not adversely affect other aspects of the system.
46
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 14. Peripheral Interface I/O Clock Timings
Clock EMCTxClk frequency EMCTxClk high time EMCTxClk low time EMCRxClk frequency EMCRxClk high time EMCRxClk low time TmrClk PerClk TCK USB1FClk (48MHz 0.05%) PWM_TBA Min 2.5 35% of nominal 35% of nominal 2.5 35% of nominal 35% of nominal na 33 na 47.976 na Max 25 - - 25 - - 100 83 20 48.024 83 Units MHz ns ns MHz ns ns MHz MHz MHz MHz MHz
Figure 4. Input Setup and Hold Timing Waveform
System Clock
1.5V TIS MIN
TIH MIN
Inputs
1.5V
Valid
Figure 5. Output Delay and Float Timing Waveform
System Clock 1.5V TOV MAX TOH MIN
Outputs
1.5V Valid MAX MIN
TOF
Outputs
1.5V
AMCC Proprietary
47
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 15. I/O Specifications--All CPU Speeds (Sheet 1 of 2)
Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter selected. 2. For all interfaces, I/O H is specified at 2.4 V and I/O L is specified at 0.4 V. 3. Maximum skew between IIC output signals is 6ns. 4. Maximum skew between all SPI output signals is 3ns. All SPI inputs signals are latched with less than 4ns of skew between channels. 5. Maximum skew between all PWM output signals is 3.75ns. All PWM input signals are latched with less than 2.5ns of skew between channels.
Input (ns) Signal Ethernet Interface EMCRxD[0:3] EMCTxD[0:3] EMCRxEr EMCMDIO EMCRxDv EMCCRS EMCTxEr EMCTxEn EMCMDC EMCCOL Internal Peripheral Interface IIC0SClk IIC0SData UART0_CTS UART0_RTS UART0_Rx UART0_Tx UART1_Rx UART1_Tx USB_FClk USB1DEV0 USB1DEV0 USB1HOST0 USB1HOST0 USB1HOST1 USB1HOST1 SPI_ClkOut SPI_DI SPI_DO SPI_SS0:3 SPI_SS_In CAN0_Rx CAN0_Tx CAN0_TxE CAN1_Rx CAN1_Tx CAN1_TxE ADC_In0:7 48 na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na IIC 2.1 IIC 2.1 na 19.1 na 19.1 na 19.1 USB 2.1 USB 2.1 USB 2.1 USB 2.1 USB 2.1 USB 2.1 USB 2.1 19.1 19.1 19.1 19.1 19.1 na 19.1 19.1 na 19.1 19.1 na IIC 2.1 IIC 2.1 na 8.7 na 8.7 na 8.7 USB 2.1 USB 2.1 USB 2.1 USB 2.1 USB 2.1 USB 2.1 USB 2.1 8.7 8.7 8.7 8.7 8.7 na 8.7 8.7 na 8.7 8.7 na AMCC Proprietary 4 4 4 na na na na na na na na 3 3 na na na na 2.5 na 2.5 na 4 na 4 na 20 20 na 2 2 na 2.5 4 20 na na na 2 na na na 19.1 19.1 na 19.1 na 19.1 19.1 19.1 19.1 19.1 8.7 8.7 na 8.7 na 8.7 8.7 8.7 8.7 8.7 EMCTxClk EMCTxClk async async EMCRxClk async EMCRxClk EMCTxClk EMCRxClk async Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) I/O H (min) I/O L (min) Clock Notes
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 15. I/O Specifications--All CPU Speeds (Sheet 2 of 2)
Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter selected. 2. For all interfaces, I/O H is specified at 2.4 V and I/O L is specified at 0.4 V. 3. Maximum skew between IIC output signals is 6ns. 4. Maximum skew between all SPI output signals is 3ns. All SPI inputs signals are latched with less than 4ns of skew between channels. 5. Maximum skew between all PWM output signals is 3.75ns. All PWM input signals are latched with less than 2.5ns of skew between channels.
Input (ns) Signal ADC_InTrig ADC_VRef DAC_CRef DAC_IOutP DAC_IPTrig DAC_IRRef DAC_VRef DAC_GRef PWM_DivClk PWM_OE[0] PWM_OE[1:3] PWM_TBA PWM_1:15 IEEE_1588TS Interrupts Interface [IRQ0:4] JTAG Interface TCK TDI TDO TMS TRST System Interface GPIO000:31 GPIO100:20 Halt SysErr SysReset TestEn DebugEn SysClk na na 22.5 na na na na na na na 0 na na na na na na na na 15 na na na na na na na 25.5 na na na na 19.1 19.1 na 19.1 19.1 na na na 8.7 8.7 na 8.7 8.7 na na na TCK TCK async async na 22.5 na 22.5 na na 0 na 0 na na na 25 na na na na 0 na na na na 19.1 na na na na 8.7 na na TCK TCK TCK TCK 19.1 8.7 na na na na na na Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) na na na na Hold Time (TOH min) na na na na Output Current (mA) I/O H (min) na na na na 19.1 na na na 19.1 19.1 19.1 19.1 19.1 19.1 I/O L (min) na na na na 8.7 na na na 8.7 8.7 8.7 8.7 8.7 8.7 5 5 5 5 5 Clock Notes
AMCC Proprietary
49
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 16. I/O Specifications--416 MHz CPU
Notes: 1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns. 2. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns) Signal Setup Time (TIS min) na na na na na na 1.6 1.6 na 1.6 na 1.6 na na Hold Time (TIH min) na na na na na na 2.1 2.1 na 2.1 na 2.1 na na 7.2 7.35 7.3 7.3 7.5 na 7.3 na 7.35 na 7.35 7.3 7.1 7.1 7.1 9.2 10 -0.7 0 7.1 7.1 na 5 na 0.9 7.3 na 0.9 0.9 2.1 na 7.1 2 2.16 2.1 2.1 2.1 na 2.1 na 2.15 na 2.15 2.15 0.9 0.9 0.9 0.9 Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) I/O H (minimum) 19.1 19.1 19.1 19.1 19.1 19.1 19.1 na 19.1 na 19.1 na 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 I/O L (minimum) 8.7 8.7 8.7 8.7 8.7 8.7 8.7 na 8.7 na 8.7 na 8.7 8.7 8.7 8.7 8.7 8.7 8.7 8.7 8.7 8.7 8.7 8.7 Clock Notes
External Peripheral Interface PerClk CRAM_Clk CRAM_AdV PerAddr04:31 BusReq PerCS0:7 PerData00:31 HoldReq HoldAck HoldPri PerOE PerReady PerRW PerWBE0:3 NFALE NFCE0 NFCLE NFData0:7 NFRB NFRE NFWE DMAAck DMAEOT/TC DMAReq na na PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk
50
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Initialization
The following describes the method by which initial chip settings are established when a system reset occurs. Strapping When the SysReset input is driven low (system reset), the state of certain I/O pins is read in order to enable default initial conditions before PPC405EZ start-up. The actual instant of capture is the nearest system clock edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. The recommended pull-up is 3k to +3.3V, or 10k to +5V. The recommended pull-down is 1K to GND. These pins are only used for strap functions during reset. They are used for other signals during normal operation. The following table lists the strapping pins along with their functions and strapping options. The signal names assigned to the pins for normal operation appear below the pin number. Table 17. Strapping Pin Assignments
Pin Strapping Function Option 8 bits wide Initialize from EBC 16 bits wide 32 bits wide 512 page, 3 addr cycle Initialize from NAND Flash 512 page, 4 addr cycle 2K page, 4 addr cycle 2K page, 5 addr cycle Initialize from SPI Reserved Slow Fast na F03 (GPIO114) 0 0 0 0 0 0 0 0 1 1 1 Initialize from IIC Note: If reading of initialization data from the IIC interface fails, the PPC405EZ defaults to strapping option 0010. 1 na 1 1 1 1 E03 (GPIO112) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D01 (GPIO111) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D02 (GPIO110) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
AMCC Proprietary
51
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Revision Log
Date 01/13/2006 Version 1.08 Initial distribution for review. Misc. corrections. Correct AMCC address. Add revision log. Change three EBC signals to match previous chips (HoldAck, HoldPri, and HoldReq). Misc. corrections. Add pull-up/pull-down notes. Update clock timings. Correct Bootstrap pin numbers. Correct pin number swaps. Add circuit types to signal descriptions. Reduce recommended logic voltage range by 0.025V. Add 266MHz and 333MHz CPU speeds. Allow 3.3V power supply for ADC and DAC. Add output currents to I/O tables. Correct Recommended Operating Conditions. Remove 5V Tolerant input current curve. Add output current values (based on I/O circuit type) to I/O tables Correct filter circuit component units-of-measure from m to . Correct ADC_In6 and ADC_In7 pins assignment. Correct EBC_Dbus24 and EBC_Dbus25 pins assignment. Change signal name NI_DivClk to PWM_DivClk. Add typical DC power requirements. Split OVDD voltage pins into two sets so EBC voltage can be different from other I/O if necessary. Update from engineering review. Timing updates. Chameleon Timer and IEEE 1588 PTP updates. Add package thermal data. Analog voltage filter updates. Part number updates. Remove TE package and references to "industrial" from thermal package data. Remove watermark and change status to Preliminary. Add heat sink data and increase case temperature range to +105C. Change minimum CPU frequency to 133.33MHz. Add DC power supply current load values. Change pin assignments for the Ethernet Tx and Rx data signals. Alter prefixes and remove extraneous characters from some signal names to make them consistent with the UM and previous chips. There are no functional or pin (ball) number changes. Correct JTAG ID. Remove CAN disable option. Reduce maximum SPI speed. Change power specifications in Description. Add link to AMCC partners supplying probes. Deleted internal clock signal timing table. Added PerClk signal to external peripheral timing table. Restrict ADC and DAC analog voltage filters to OVDD1. Typographical Updates Contents of Modification
03/09/2006
1.09
04/10/2006
1.10
04/21/2006
1.11
05/12/2006
1.12
06/13/2006 07/18/2006 08/8/2006
1.13 1.14 1.15
08/30/2006
1.16
09/05/2006
1.17
09/18/2006
1.18
10/18/2006
1.19
02/07/2007
1.20
52
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Date 02/20/2007 02/21/2007 02/27/2007 03/05/2007 04/02/2007 04/23/2007 08/22/2007 Version 1.21 1.22 1.23 1.24 1.25 1.26 1.27 Contents of Modification The VCOFc minimal value in the System Clock Specification in Table 13: Changed to 600 MHz instead of 66 Changes to the UART section and the Ethernet section Added a sentence to the NAND Flash Controller section Change picture on page 16. Added a overline on the signal CRAM_AdV. Changed the PVR value on page 4 Added missing information to table 14.
AMCC Proprietary
53
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Applied Micro Circuits Corporation 215 Moffett Park Drive, Sunnyvale, CA 94089 Phone: (858) 450-9333 -- (800) 755-2622 -- Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available datasheet. Please consult AMCC's Term and Conditions of Sale for its warranties and other terms, conditions and limitations. AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright (c) 2007 Applied Micro Circuits Corporation.
54
AMCC Proprietary

▲Up To Search▲

Price & Availability of PPC405EZ-CSAFFFTX

	To Download PPC405EZ-CSAFFFTX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .